翟建旺，北京邮电大学特聘副研究员，硕士生导师。2018年于北京交通大学通信工程（试点班）专业获学士学位，2023年于清华大学计算机科学与技术专业获博士学位，同年经人才引进至北京邮电大学集成电路学院。

主要研究方向为人工智能赋能集成电路设计自动化（EDA），聚焦于处理器体系结构、综合及编译优化、集成电路物理设计等方向的研究。近年来，以第一作者或通讯作者在TCAD、TVLSI、TCAS、TODAES、DAC、ICCAD、DATE、ASP-DAC、AAAI等高水平国际期刊/会议上发表20余篇论文，曾荣获ICCAD 2021最佳论文奖、ASP-DAC 2023最佳论文奖提名、EDA²最佳博士学位论文奖。主持GF科技国家级项目、国家自然科学基金、北京市自然科学基金等项目，并作为骨干参与国家重点研发计划、国家自然科学基金重点等项目。

 个人主页：https://zhaijw18.github.io/

欢迎计算机、人工智能、集成电路、电子信息、数学等相关背景的同学联系。

研究领域

1. 人工智能及其在集成电路设计自动化中的应用；

2. 体系结构：处理器微架构建模、设计空间探索、综合及编译优化、面向Chiplet的EDA等；

3. 集成电路物理设计与验证：布图规划、布局布线、电迁移与电压降分析等。

代表性成果

[1] Jianwang Zhai, Chen Bai, Binwu Zhu, Yici Cai, Qiang Zhou, and Bei Yu, McPAT-Calib: A RISC-V BOOM Microarchitecture Power Modeling Framework, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 42, no. 01, pp. 243–256, 2023.

[2] Jianwang Zhai, Yici Cai, Microarchitecture Design Space Exploration via Pareto-driven Active Learning, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 31, no. 11, pp. 1727-1739, 2023.

[3] Jianwang Zhai, Yici Cai, and Qiang Zhou, Placement and Routing Methods Considering Shape Constraints of JTL for RSFQ Circuits, IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II), vol. 68, no. 5, pp. 1571-1575, 2021.

[4] Jianwang Zhai, Chen Bai, Binwu Zhu, Yici Cai, Qiang Zhou, and Bei Yu, McPAT-Calib: A Microarchitecture Power Modeling Framework for Modern CPUs, IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Nov, 1-4, 2021, pp.1-9.

[5] Jianwang Zhai, Yici Cai, and Bei Yu, Microarchitecture Power Modeling via Artificial Neural Network and Transfer Learning, IEEE/ACM Asian and South Pacific Design Automation Conference (ASP-DAC), Jan. 16-19, 2023, pp. 1-6. (Best Paper Award Nomination)

[6] Jianwang Zhai, Zichao Ling, Chen Bai, Kang Zhao, Bei Yu, “Machine Learning for Microarchitecture Power Modeling and Design Space Exploration: A Survey ”, Journal of Computer Research and Development (J-CRAD), vol. 61, no. 06, pp. 1-19, 2024. (in Chinese)

[7] Yuyang Ye, Mingwei He, Lizheng Ren, Jianwang Zhai#, Tinghuan Chen, Jun Yang, Longxing Shi, “Truly Pre-Routing Timing Prediction via Considering Power Delivery Networks”, ACM/IEEE Design Automation Conference (DAC), San Francisco, Jun. 22–25, 2025.

[8] Feng Guo, Yueyue Xi, Jianwang Zhai#, Jingyu Jia, Jiawei Liu, Kang Zhao, Chuan Shi#, “IRGNN: A Graph-based Framework Integrating Numerical Solution and Point Cloud for Static IR Drop Prediction”, ACM/IEEE Design Automation Conference (DAC), San Francisco, Jun. 22–25, 2025.

[9] Chen Bai, Jianwang Zhai#, Yuzhe Ma, Bei Yu#, Martin D.F. Wong, Towards Automated RISC-V Microarchitecture Design with Reinforcement Learning, AAAI Conference on Artificial Intelligence (AAAI), Vancouver, Feb. 20-27, 2024.

[10] Jiawei Liu, Jianwang Zhai#, Mingyu Zhao, Zhe Lin, Bei Yu, Chuan Shi#, “PolarGate: Breaking the Functionality Representation Bottleneck of And-Inverter Graph Neural Network”, IEEE/ACM International Conference on Computer-Aided Design (ICCAD), New Jersey, Oct. 27-31, 2024.

[11] Jiawei Liu, Zhiyan Liu, Xun He, Jianwang Zhai#, Zhengyuan Shi, Qiang Xu, Bei Yu, Chuan Shi#, “WideGate: Beyond Directed Acyclic Graph Learning in Subcircuit Boundary Prediction”, IEEE/ACM Proceedings Design, Automation and Test in Europe (DATE), Lyon, France, Mar. 31–Apr. 02, 2025.

[12] Feng Guo, Jianwang Zhai#, Jingyu Jia, Jiawei Liu, Kang Zhao, Bei Yu, Chuan Shi#, “IR-Fusion: A Fusion Framework for Static IR Drop Analysis Combining Numerical Solution and Machine Learning”, IEEE/ACM Proceedings Design, Automation and Test in Europe (DATE), Lyon, France, Mar. 31–Apr. 02, 2025.

[13] Jingyu Jia, Jianwang Zhai#, Kang Zhao, Fast Estimation for Electromigration Nucleation Time Based on Random Activation Energy Model, IEEE/ACM Proceedings Design, Automation and Test in Europe (DATE), Valencia, Spain, Mar. 25-27, 2024.

[14] Shixin Chen, Hengyuan Zhang, Zichao Ling, Jianwang Zhai#, Bei Yu#, “The Survey of 2.5D Integrated Architecture: An EDA perspective”, IEEE/ACM Asian and South Pacific Design Automation Conference (ASP-DAC), Tokyo, Jan. 20-23, 2025. (Invited Paper)

[15] Zirui Li*, Kanglin Tian*, Jianwang Zhai#, Zixuan Li, Shixiong Kai, Siyuan Xu, Bei Yu, Kang Zhao, “FTAFP: A Feedthrough-Aware Floorplanner for Hierarchical Design of Large-Scale SoCs”, IEEE/ACM Asian and South Pacific Design Automation Conference (ASP-DAC), Tokyo, Jan. 20-23, 2025.

[16] Guande Dong*, Jianwang Zhai*#, Hongtao Cheng, Xiao Yang, Chuan Shi, Kang Zhao#, “PIRLLS: Pretraining with Imitation and RL Finetuning for Logic Synthesis”, IEEE/ACM Asian and South Pacific Design Automation Conference (ASP-DAC), Tokyo, Jan. 20-23, 2025.

[17] Feng Guo*, Jiawei Liu*, Jianwang Zhai#, Jingyu Jia, Kang Zhao, Chuan Shi#, “PGAU: Static IR Drop Analysis for Power Grid using Attention U-Net Architecture and Label Distribution Smoothing”, ACM Great Lakes Symposium on VLSI (GLSVLSI), FL, USA, Jun. 12-14, 2024.

[18] Zixuan Li*, Kanglin Tian*, Jianwang Zhai#, Zirui Li, Kang Zhao, “HieRFP: A Hierarchical Recognition and Floorplanning Framework for Reusable Modules”, IEEE International Symposium on Circuits and Systems (ISCAS), London, UK, May. 25–28, 2025.

[19] Zirui Li, Jianwang Zhai#, Zixuan Li, Zhongdong Qi, Kang Zhao, “Effective Resource Model and Cost Scheme for Maze Routing in 3D Global Routing”, IEEE International Symposium on Circuits and Systems (ISCAS), Singapore, May. 19-22, 2024.

[20] Chen Bai, Qi Sun, Jianwang Zhai, Yuzhe Ma, Bei Yu, MD Wong, BOOM-Explorer: RISC-V BOOM Microarchitecture Design Space Exploration Framework, IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Nov. 01–04, 2021. (William J. McCalla Best Paper Award)